1. Technical Field
The present invention relates generally to the field of semiconductor processing and, more specifically, to a fabrication process for a transistor structure with thick recessed source/drain (S/D) structures.
2. Background Art
The need to remain cost and performance competitive in the production of semiconductor devices has caused continually increasing device density in integrated circuits. To facilitate the increase in device density, new technologies are constantly needed to allow the feature size of these semiconductor devices to be reduced.
The push for ever increasing device densities is particularly strong in CMOS technologies, such as the in the design and fabrication of field effect transistors (FETs). FETs are the basic electrical devices of today's integrated circuits and are used in almost all types of integrated circuit design (i.e., microprocessors, memory, etc.). FETs may be formed on conventional substrates such as a silicon wafer. For example, a conventional CMOS FET formed on a silicon wafer may include a gate oxide layer formed on the wafer, a gate formed on the gate oxide layer, spacers formed beside the gate on the gate oxide layer, and doped S/D regions arranged on respective sides of a gate conductor. The gate is separated from a channel (which is situated between the source and drain regions) by the gate oxide layer. Shallow trench insulator (STI), local oxidation of silicon (LOCOS), or poly-buffered LOCOS isolations are usually employed to provide for isolation of adjacent transistors.
Unfortunately, increased device density in FETs often results in degradation of performance and/or reliability. One type of FET that has been proposed to facilitate increased device density is a double gated FET (fin FET). Fin FETs use two gates, one on each side of a fin structure, to facilitate scaling of CMOS dimensions for example, while maintaining an acceptable performance. In particular, the use of the double gate increases gate area, which allows the fin FET to have higher current, without increasing the lateral dimensions of the device.
Additionally, with increased device density in FETs, it is difficult to improve various performances of semiconductor devices using a bulk wafer. Semiconductor devices are made with thinner layers that have more abrupt transitions between the layers. Therefore, semiconductor devices using a silicon-on-insulator (SOI) wafer will play a greater role in device structuring in the future. Conventional SOI construction methods involve the formation of silicon devices on a thin film of single crystalline silicon material separated from a wafer of silicon material by a layer of buried oxide (BOX).
However, a good, low resistant contact from the source/drain regions to the channel in a thin SOI film are difficult to make. Conventional methods attempt to solve this problem by raising the source/drain (S/D) regions on either side of the transistor resulting in low S/D resistance. However, this in turn increases the capacitance between the gate and the S/D regions because of the close proximity of the S/D contact to the gate (e.g. S/D silicon abutting the sides of the gate). Therefore, this increase in gate-to-S/D capacitance leads to a decrease in device performance. This is one of the limiting factors for SOI device performance.
Thus, there is a need for improved transistor structures and methods of fabrication of transistor structures that provide transistors with S/D regions that provide low S/D resistance without increasing gate-to-S/D capacitance.